Switched Shunt Model: ABBSVC1
AutoCorrection Properties
Following checks and corrections are applied during Validation and AutoCorrection.
- If 0.0 < T4< 0.5*Mult*TimeStep then T4= Mult*TimeStep
- If 0.0 < T7< 0.5*Mult*TimeStep then T7= Mult*TimeStep
- If 0.0 < T9< 0.5*Mult*TimeStep then T9= Mult*TimeStep
- If 0.0 < T11< 0.5*Mult*TimeStep then T11= Mult*TimeStep
- If 0.0 < TBReg < 0.5*Mult*TimeStep then TBReg = Mult*TimeStep
- If 0.0 < TLL2< 0.5*Mult*TimeStep then TLL2= 0, ElseIf 0.5*Mult*TimeStep < TLL2< Mult*TimeStep then TLL2= Mult*TimeStep
- If B2MAX< B2MIN then swap the values
- If BMAXDes < BMINDes then swap the values
- If BMAXDes2 < BMINDes2 then swap the values
- If VPODMAX < VPODMIN then swap the values
Mult represents the user-specified value Minimum time constant size as multiple of time step option on the Validation page of the Transient Stability Dialog
TimeStep represents the integration time step being used as described on TimeStep
Following treatment is handled during the transient numerical simulation
- If B1> B1MAX, then B1MAX= B1 or if B1 < B1MIN or , then B1MIN = B1
- If VPOD > VPODMAX, then VPODMAX= VPOD or if VPOD < VPODMIN , then VPODMIN = VPOD
- If V2 > V2Max then V2Max = V2
- IF I1 > I1MAXClim then IMAXClim = I1
- IF I1 > then ITCRMAX = I1
- If I1 < IMINI then IMINI = I1
Model Equations and/or Block Diagrams
Parameters:
| RPC | reactive power control flag; 0: Non; 1: Supplementary Control; 2: External Caps; 3: Supplementary + External Caps |
| PODStatus | flag to indicate status of aux. signal; 0: None; 1: Supplementary Control; 2: External Caps; 3: Supplementary + External Caps |
| ENABIN | flag to indicate if sign of the aux. signal to be changed or not; 1: Change POD output sign when input signal becomes negative; 0: Do not change sign |
| SVCBASE | Base MVA (>0) |
| T4 | Integrator time constant (s) (>0) |
| Ts | Thyristor firing delay (s) |
| Tth | Thyristor firing time constant (s) |
| Xcc | Slope for capacitive range, on SVC base (pu voltage/pu current) |
| Xci | Slope for inductive range, on SVC base (pu voltage/pu current) |
| TLL1 | Voltage controller lead time constant (s) |
| TLL2 | Voltage controller lag time constant (s) |
| B1MAX | max. limit for voltage controller (pu on SVC base) |
| B1MIN | min. limit for voltage controller (pu on SVC base) |
| B2MAX | max. susceptance of SVC (pu on SVC base) |
| B2MIN | min. susceptance of SVC (pu on SVC base) |
| OVThrsld | overvoltage tripping threshold (pu) |
| OVDelay | overvoltage tripping delay (s) |
| SVLow | severe undervoltage strategy low voltage threshold (pu) |
| SVHigh | severe undervoltage strategy high voltage threshold (pu) |
| SBFClear | severe undervoltage strategy susceptance (pu on SVC base) |
| STBFClear | timing of severe undervoltage strategy (s) |
| VLow | undervoltage strategy low voltage threshold (pu) |
| VHigh | undervoltage strategy high voltage threshold (pu) |
| USDelay | undervoltage strategy delay (s) |
| BFClear | undervoltage strategy susceptance (pu on SVC base) |
| TBFClear | timing of undervoltage strategy (s) |
| V2Max | max. SVC bus voltage limit (pu) |
| K6 | controller (V2) gain (pu) |
| T6 | controller (V2) time constant (s) |
| T7 | controller (V2) integrator time constant (s) (>0) |
| V2Clim | controller (V2) minimum limit (pu on SVC base) (<0) |
| I1MAXC | maximum capacitive current limit (pu on SVC base) (>0) |
| K8 | controller (I1MAXC) gain (pu) |
| T8 | controller (I1MAXC) time constant (s) |
| T9 | controller (I1MAXC) integrator time constant (s) (>0) |
| IMAXClim | controller (I1MAXC) minimum limit (pu on SVC base) (<carat0) |
| IMINI | maximum inductive current limit (pu on SVC base) (<carat0) |
| K10 | controller (I1MINI) gain (pu) |
| T10 | controller (I1MINI) time constant (s) |
| T11 | controller (I1MINI)s integrator time constant (s) (>0) |
| IMINClim | controller (I1MINI) minimum limit (pu on SVC base) (>0) |
| ITCRMAX | maximum TCR current limit (pu on SVC base) (≥ 0) |
| K1 | controller (ITCR) gain (pu) |
| T1 | controller (ITCR) time constant (s) |
| T2 | controller (ITCR) integrator time constant (s) (>0) |
| TCRLimTRG | TCR current limiter voltage trigger (pu) |
| TCRMIN | minimum TCR limit for ITCR control (pu on SVC base) |
| FShunt | fixed shunt compensation (pu on SVC base) (≥ 0) (this is always the filters, which are always capacitive; hence≥ zero) |
| BRegMAX | supplementary control capacitive threshold (pu on SVC base) |
| BRegMIN | supplementary control inductive threshold (pu on SVC base) |
| VRefMAX | maximum reference voltage for regulated bus voltage (pu) |
| VRefMIN | minimum reference voltage for regulated bus voltage (pu) |
| TBReg | integrator time constant for supplementary control(s) (>0) |
| DVBRegMAX | max. output of supplementary control (pu) |
| DVBRegMIN | min. output of supplementary control (pu) |
| BMAXDes | MSC slow switching capacitive threshold (pu on system base) |
| BMINDes | MSC slow switching inductive threshold (pu on system base) |
| TDelay1 | time delay for slow switching of MSCs (s) |
| BMAXDes2 | MSC fast switching capacitive threshold (pu on system base) |
| BMINDes2 | MSC fast switching inductive threshold (pu on system base) |
| TDelay2 | time delay for fast switching of MSCs, (s) |
| PODTW1 | washout filter 1 time constant (s) (if zero, the washout is disabled) |
| PODTW2 | washout filter 1 time constant (s) (>0) (if zero, the washout is disabled) |
| PODTM1 | POD 1st lead-lag block lead time constant (s) |
| PODTM2 | POD 1st lead-lag block lag time constant (s) |
| PODTM3 | POD 2nd lead-lag block lead time constant (s) |
| PODTM4 | POD 2nd lead-lag block lag time constant (s) |
| PODTM5 | 3rd POD lead-lag block lead time constant (s) |
| PODTM6 | 3rd POD lead-lag block lag time constant (s) |
| KPOD | POD gain (pu) |
| VPODMAX | POD max. output limit (pu) |
| VPODMIN | POD min. output limit (pu) |
| PODTW4 | washout filter 4 time constant (s) |